View SA7025_4792478.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

SA7025 low-voltage 1ghz fractional-n synthesizer product specification 1996 aug 6 integrated circuits ic17 data handbook
philips semiconductors product specification SA7025 1ghz low-voltage fractional-n synthesizer 2 1996 aug 6 853-1786 17157 description the SA7025 is a monolithic low power, high performance dual frequency synthesizer fabricated in qubic bicmos technology. featuring fractional-n division with selectable modulo 5 or 8 implemented in the main synthesizer to allow the phase detector comparison frequency to be five or eight times the channel spacing. this feature reduces the overall division ratio yielding a lower noise floor and faster channel switching. the phase detectors and charge pumps are designed to achieve phase detector comparison frequencies up to 5mhz. a triple modulus prescaler (divide by 64/65/72) is integrated on chip with a maximum input frequency of 1.04ghz. programming and channel selection are realized by a high speed 3-wire serial interface. features ? operation up to 1.04ghz ? fast locking by afractional-no divider ? auxiliary synthesizer ? digital phase comparator with proportional and integral charge pump output ? high speed serial input ? low power consumption ? programmable charge pump currents ? supply voltage range 2.7 to 5.5v ? excellent input sensitivity: v rf_in = 20dbm applications ? nadc (north american digital cellular) ? pdc (personal digital cellular) ? cellular radio ? spread-spectrum receivers pin configuration v ss data clock dk package 1 2 3 4 5 6 7 8 9 10 11 12 13 14 20 19 18 17 16 15 strobe ra test v dd rf rn pha v dda php v ssa phi lock rf in rf in v ccp ref in aux in sr00600 figure 1. pin configuration ordering information description temperature range order code dwg # 20-pin plastic shrink small outline package (ssop) 40 to +85 c SA7025dk sot266-1 absolute maximum ratings symbol parameter rating units v supply voltage, v dd , v dda , v ccp -0.3 to +6.0 v v in voltage applied to any other pin -0.3 to (v dd + 0.3) v t stg storage temperature range -65 to +150 c t a operating ambient temperature range -40 to +85 c note: thermal impedance ( q ja ) = 117 c/w. this device is esd sensitive.
philips semiconductors product specification SA7025 1ghz low-voltage fractional-n synthesizer 1996 aug 6 3 pin descriptions symbol pin description clock 1 serial clock input data 2 serial data input strobe 3 serial strobe input v ss 4 digital ground rf in 5 prescaler positive input rf in 6 prescaler negative input v ccp 7 prescaler positive supply voltage. this pin supplies power to the prescaler and rf input buffer ref in 8 reference divider input ra 9 auxiliary current setting; resistor to v ssa aux in 10 auxiliary divider input pha 11 auxiliary phase detector output v ssa 12 analog ground phi 13 integral phase detector output php 14 proportional phase detector output v dda 15 analog supply voltage. this pin supplies power to the charge pumps, auxiliary prescaler, auxiliary and reference buffers. rn 16 main current setting; resistor to v ssa rf 17 fractional compensation current setting; resistor to v ssa lock 18 lock detector output test 19 test pin; connect to v dd v dd 20 digital supply voltage. this pin supplies power to the cmos digital part of the device
philips semiconductors product specification SA7025 1ghz low-voltage fractional-n synthesizer 1996 aug 6 4 block diagram serial input + program latches main dividers prescaler modulus normal output charge pump integral output charge pump auxiliary output charge pump main phase detector main reference select speed-up output charge pump reference divider 2 2 2 auxiliary reference select auxiliary phase detector auxiliary divider 1/4 data clock strobe rf in rf in ref in aux in fb rf rn php phi ra pha lock v dd v dda v ss v ssa em pr nm1 nm2 nm3 fmod nf 2 12 8 3 frd cn 8 2 2 em nr em+ea 12 sa ea pa na 2 4 sm ea 2 ck cl 2 12 fractional accumulator 64/65/72 fb test v ccp prescaler 2 control prescaler sr00601 figure 2. block diagram
philips semiconductors product specification SA7025 1ghz low-voltage fractional-n synthesizer 1996 aug 6 5 dc electrical characteristics v dd = v dda = v ccp = 3v; t a = 25 c, unless otherwise specified. symbol parameter test conditions limits units symbol parameter test conditions min typ max units v supply recommended operating conditions v ccp = v dd , v dda v dd 2.7 5.5 v i standby total standby supply currents em = ea = 0, i rn = i rf = i ra = 0 50 500 m a operational supply currents: i = i dd + i ccp + i dda ; i rn = 25 m a, i ra = 25 m a, (see note 5) i aux operational supply currents em = 0, ea = 1 3.5 ma i main operational supply currents em = 1, ea = 0 5.5 ma i total operational supply currents em = ea = 1 7.5 ma digital inputs clk, data, strobe v ih high level input voltage range 0.7xv dd v dd v v il low level input voltage range 0 0.3xv dd v digital outputs lock v ol output voltage low i o = 2ma 0.4 v v oh output voltage high i o = 2ma v dd 0.4 v charge pumps: v dda = 3v / i rx = 25 m a or v dda = 5v / i rx = 62.5 m a, v phx in range, unless otherwise specified. (see note 16) |i | setting current range for any setting re- 2.7v < v dda < 5.5v 25 m a |i rx | ggyg sistor 4.5v < v dda < 5.5v 62.5 m a v phout output voltage range 0.7 v dda 0.8 v charge pump pha |i | out p ut current pha i ra = 62.5 m a; v pha = v dda /2 13 400 500 600 m a |i pha | o u tp u t c u rrent pha i ra = 25 m a; v pha = v dda /2 160 200 240 m a i php_a |i php_a | relative output current variation pha i ra = 62.5 m a 2, 13 2 6 % d i out p ut current matching pha p um p v dda = 3v, i ra = 25 m a 50 m a d i pha_m o u tp u t c u rrent matching pha p u mp v dda = 5v, i ra = 62.5 m a 65 m a charge pump php, normal mode 1, 4, 6 v rf = v dda |i | out p ut current php i rn = 62.5 m a; v php = v dda /2 13 440 550 660 m a |i php_n | o u tp u t c u rrent php i rn = 25 m a; v php = v dda /2 175 220 265 m a i php_n i php_n relative output current variation php i rn = 62.5 m a 2, 13 2 6 % d i output current matching php v dda = 3v, i ra = 25 m a 50 m a d i php_n_m g normal mode v dda = 5v, i ra = 62.5 m a 65 m a charge pump php, speed-up mode 1, 4, 7 v rf = v dda |i s | out p ut current php i rn = 62.5 m a; v php = v dda /2 13 2.20 2.75 3.30 ma |i php_s | o u tp u t c u rrent php i rn = 25 m a; v php = v dda /2 0.85 1.1 1.35 ma i php_s i php_s relative output current variation php i rn = 62.5 m a 2, 13 2 6 % d i s output current matching php v dda = 3v, i ra = 25 m a 250 m a d i php_s_m g speed-up mode v dda = 5v, i ra = 62.5 m a 300 m a charge pump phi, speed-up mode 1, 4, 8 v rf = v dda |i | out p ut current phi i rn = 62.5 m a; v phi = v dda /2 13 4.4 5.5 6.6 ma |i phi | o u tp u t c u rrent phi i rn = 25 m a; v phi = v dda /2 1.75 2.2 2.65 ma i phi i phi relative output current variation phi i rn = 62.5 m a 2, 13 2 8 % d i out p ut current matching phi p um p v dda = 3v, i ra = 25 m a 500 m a d i phi_m o u tp u t c u rrent matching phi p u mp v dda = 5v, i ra = 62.5 m a 600 m a fractional compensation php, normal mode 1, 9 v rn = v dda , v php = v dda /2 i fractional compensation output current i rf = 62.5 m a;f rd = 1 to 7 13 625 400 250 na i php_f_n php vs f rd 3 i rf = 25 m a;f rd = 1 to 7 250 180 100 na
philips semiconductors product specification SA7025 1ghz low-voltage fractional-n synthesizer 1996 aug 6 6 dc electrical characteristics (continued) symbol parameter test conditions limits units symbol parameter test conditions min typ max units fractional compensation php, speed up mode 1, 10 v php = v dda , v rn = v dda i s fractional compensation output current i rf = 62.5 m a;f rd = 1 to 7 13 3.35 2.0 1.1 m a i php_f_s php vs f rd 3 i rf = 25 m a;f rd = 1 to 7 1.35 1.0 0.5 m a pump leakage 20 20 na fractional compensation phi, speed up mode 1, 11 v php = v dda /2, v rn = v dda i fractional compensation output current i rf = 62.5 m a;f rd = 1 to 7 13 5.4 4.0 2.6 m a i phi_f phi vs f rd 3 i rf = 25 m a;f rd = 1 to 7 2.15 1.6 1.05 m a charge pump leakage currents, charge pump not active i php_l output leakage current php; normal mode 1 v php = 0.7 to v dda 0.8 0.1 10 na i phi_l output leakage current phi; normal mode 1 v phi = 0.7 to v dda 0.8 0.1 10 na i pha_l output leakage current pha v pha = 0.7 to v dda 0.8 0.1 10 na ac electrical characteristics v dd = v dda = v ccp = 3v; t a = 25 c; f rf_in = 1ghz, input level = 20dbm; unless otherwise specified. test circuit, figure 4. the parameters listed below are tested using automatic test equipment to assure consistent electrical characteristics. the limits do not repr esent the ultimate performance limits of the device. use of an optimized rf layout will improve many of the listed parameters. symbol parameter test conditions limits units symbol parameter test conditions min typ max units main divider f in p ut signal frequency direct coupled input 14 1.04 ghz f rf_in inp u t signal freq u enc y 1000pf input coupling 1.04 gh z v rf_in input sensitivity 1040mhz 20 0 dbm reference divider (v dd = v dda = 3v or v dd = 3v / v dda = 5v) f in p ut signal frequency 2.7 < v dd and v dda < 5.5v 25 mhz f ref_in inp u t signal freq u enc y 2.7 < v dd and v dda < 4.5v 30 mh z v in p ut signal range ac cou p led 2.7 < v dd and v dda < 5.5v 500 mv v ref_in inp u t signal range , ac co u pled 2.7 < v dd and v dda < 4.5v 300 mv p-p z reference divider in p ut im p edance 15 100 k w z ref_in reference di v ider inp u t impedance 15 3 pf auxiliary divider input signal frequency 0 50 f pa = a0o, prescaler enabled 4.5v v dda 5.5v 0 150 mhz f aux_in input signal frequency 0 30 mh z pa = a1o, prescaler disabled 4.5v v dda 5.5v 0 40 v aux_in input signal range, ac coupled 200 mv p-p z auxiliary divider in p ut im p edance 100 k w z aux_in a ux iliar y di v ider inp u t impedance 3 pf serial interface 15 f clock clock frequency 10 mhz t su set-up time: data to clock, clock to strobe 30 ns t h hold time; clock to data 30 ns t pulse width; clock 30 ns t w pulse width; strobe b, c, d, e words 30 ns in-loop performance 17 v dda = 5v, v dd = 2.7v r mm main loop residual fm fvco = 1030mhz 300 600 hz
philips semiconductors product specification SA7025 1ghz low-voltage fractional-n synthesizer 1996 aug 6 7 ac electrical characteristics (continued) symbol parameter test conditions limits units symbol parameter test conditions min typ max units t sw pulse width ; strobe a word, pr = `01' 1 f vco (nm2 65) t w ns t sw pulse width strobe a word, pr = `10' 1 f vco [(nm2 65) (nm3 1) 72] t w ns notes: 1. when a serial input aao word is programmed, the main charge pumps on php and phi are in the aspeed up modeo as long as strobe = h. when this is not the case, the main charge pumps are in the anormal modeo. 2. the relative output current variation is defined thus: i out i out 2 (i 2 i 1 ) |(i 2 i 1 )| ; with v 1 = 0.7v, v 2 = v dda 0.8v (see figure 3). 3. f rd is the value of the 3 bit fractional accumulator. 4. monotonicity is guaranteed with c n = 0 to 255. 5. power supply current measured with v dd = v ccp = 3v, v dda = 5v, f rf in = 915.99mhz, xtal at 21.36mhz, aux at 85.92mhz (pa = `0'), main comp frequency = 240khz, auxiliary comp frequency = 120khz, cn = 160, cl = 0, ck = 0. internal registers nm1 = 52, nm2 = 0, nm3 = 4, pr = `10', sm = `00', sa = `01', na = 179, nf = 5, fmod = 8, nr = 89, pa = 0, irn = ira = irf = 25 m a, lock condition, normal mode. operational supply current = i dda + i dd + i ccp . 6. specification condition: cn = 255 7. specification conditions: 1) cn = 255; cl = 1, or 2) cn = 75; cl = 3 8. typical output current | i phi | = i rn x cn x 2 (cl+1) x ck/32: 1) cn = 160; cl = 3; ck = 1, or 2) cn = 160; cl = 2; ck = 2, or 3) cn = 160; cl = 1; ck = 4, or 4) cn = 160; cl = 0; ck = 8 9. any rfd, cl = 1 for speed-up pump. the integral pump is intended for switching only and the fractional compensation is not g uaranteed. 10. specification conditions: f rd = 1 to 7; cl = 1. 11. specification conditions: 1) f rd = 1 to 7; cl = 1; ck = 2, or 2) f rd = 1 to 7; cl = 2; ck = 1. 12. the matching is defined by the sum of the p and the n pump for a given output voltage. 13. limited analog supply voltage range 4.5 to 5.5v. 14. for f in < 50mhz, low frequency operation requires dc-coupling and a minimum input slew rate of 32v/ m s. 15. guaranteed by design. 16. close in noise for the charge pumps is tested on a sample basis in a typical application in order to eliminate parts outside the normal distribution. 17. f xtal = 14.4mhz, v xtal = 500mv p-p , comparison frequency = 200khz, loop bandwidth = 5khz, audio filter = 300hz to 15khz.
philips semiconductors product specification SA7025 1ghz low-voltage fractional-n synthesizer 1996 aug 6 8 i 2 i 1 i 2 i 1 v 1 v 2 current voltage sr00602 figure 3. relative output current variation 1 2 3 4 5 6 7 8 9 10 11 12 13 14 20 19 18 17 16 15 clock data strobe v ss rf in rf in v ccp ref in ra aux in v dd test lock rf rn v dda php phi v ssa pha SA7025 v dd a v ph p v phi v ph a v dd clock data strobe rf in rf in v ccp ref in aux in 150k test 22nf rf 150k 22nf 1k rn 100 1k 22nf 50 50 22nf 22nf 150k 22nf 22nf 50 50 10 m f 10 m f 10 m f lock 10k sr00603 figure 4. test circuit
philips semiconductors product specification SA7025 1ghz low-voltage fractional-n synthesizer 1996 aug 6 9 ac timing characteristics data d0 d1 t sw clock strobe clock enabled clock disabled store data shift in data clock strobe (b, c, d, e) words strobe (a word) t w 50% 50% t su last clock first clock first clock 50% t su t h t su d0 d22, d30 d23, d31 sr00604 figure 5. serial input timing sequence functional description serial input programming the serial input is a 3-wire input (clock, strobe, data) to program all counter ratios, dacs, selection and enable bits. the programming data is structured into 24 or 32 bit words; each word includes 1 or 4 address bits. figure 5 shows the timing diagram of the serial input. when the strobe = l, the clock driver is enabled and on the positive edges of the clock the signal on data input is clocked into a shift register. when the strobe = h, the clock is disabled and the data in the shift register remains stable. depending on the 1 or 4 address bits the data is latched into different working registers or temporary registers. in order to fully program the synthesizer, 4 words must be sent: d, c, b and a. figure 6 and table 1 shows the format and the contents of each word. the e word is for testing purposes only. the e (test) word is reset when programming the d word. the data for cn and pr is stored by the b word in temporary registers. when the a word is loaded, the data of these temporary registers is loaded together with the a word into the work registers which avoids false temporary main divider input. cn is only loaded from the temporary registers when a short 24 bit a0 word is used. cn will be directly loaded by programming a long 32 bit a1 word. the flag long in the d word determines whether a0 (long = a0o) or a1 (long = a1o) format is applicable. the a word contains new data for the main divider. main divider synchronization the a word is loaded only when a main divider synchronization signal is also active in order to avoid phase jumps when reprogramming the main divider. the synchronization signal is generated by the main divider. the signal is active while the nm1 divider is counting down from the programmed value. the new a word will be loaded after the nm1 divider has reached its terminal count; also, at this time a main divider output pulse will be sent to the main phase detector. the loading of the a word is disabled while the nm2 or nm3 dividers are counting up to their programmed values. therefore, the new a word will be correctly loaded provided that the strobe signal has been at an active high value for at least a minimum number of vco input cycles at rf in or rf in . t_strobe_min 1 f vco (nm 2 65) t w for pr `01 t_strobe_min 1 f vco [nm 2 65 (nm 3 1) 72] t w for pr `10 programming the a word means also that the main charge pumps on output php and phi are set into the speed-up mode as long as the strobe is h. auxiliary divider the input signal on aux_in is amplified to logic level by a single-ended cmos input buffer, which accepts low level ac coupled input signals. this input stage is enabled if the serial control bit ea = a1o. disabling means that all currents in the input stage are switched off. a fixed divide by 4 is enabled if pa = a0o. this divider has been optimized to accept a high frequency input signal. if pa = a1o, this divider is disabled and the input signal is fed directly to the second stage, which is a 12-bit programmable divider with standard input frequency (40mhz). the division ratio can be expressed as: if pa = a0o: n = 4 x na if pa = a1o: n = na; with na = 4 to 4095 reference divider the input signal on ref_in is amplified to logic level by a single-ended cmos input buffer, which accepts low level ac coupled input signals. this input stage is enabled by the or function of the serial input bits ea and em. disabling means that all currents in the input stage are switched off. the reference divider consists of a programmable divider by nr (nr = 4 to 4095) followed by a three bit binary counter. the 2 bit sm register (see figure 7) determines which of the 4 output pulses is selected as the main
philips semiconductors product specification SA7025 1ghz low-voltage fractional-n synthesizer 1996 aug 6 10 phase detector input. the 2 bit sa register determines the selection of the auxiliary phase detector signal. main divider the differential inputs are amplified (to internal ecl logic levels) and provide excellent sensitivity (20dbm at 1ghz) making the prescaler ideally suited to directly interface to a vco as integrated on the sa620 rf gain stage, vco and mixer device. the internal triple modulus prescaler feedback loop fb controls the selection of the divide by ratios 64/65/72, and reduces the minimum system division ratio below the typical value required by standard dual modulus (64/65) devices. this input stage is enabled when serial control bit em = a1o. disabling means that all currents in the prescaler are switched off. the main divider is built up by a 12 bit counter plus a sign bit. depending on the serial input values nm1, nm2, nm3, and the prescaler select pr, the counter will select a prescaler ratio during a number of input cycles according to table 2 and table 3. the loading of the work registers nm1, nm2, nm3 and pr is synchronized with the state of the main counter, to avoid extra phase disturbance when switching over to another main divider ratio as explained in the serial input programming section. at the completion of a main divider cycle, a main divider output pulse is generated which will drive the main phase comparator. also, the fractional accumulator is incremented with nf. the accumulator works modulo q. q is preset by the serial control bit fmod to 8 when fmod = a1o. each time the accumulator overflows, the feedback to the prescaler will select one cycle using prescaler ratio r2 instead of r1. as shown above, this will increase the overall division ratio by 1 if r2 = r1 + 1. the mean division ratio over q main divider will then be nq n nf q programming a fraction means the prescaler with main divider will divide by n or n + 1. the output of the main divider will be modulated with a fractional phase ripple. this phase ripple is proportional to the contents of the fractional accumulator frd, which is used for fractional current compensation. phase detectors the auxiliary and main phase detectors are a two d-type flip-flop phase and frequency detector shown in figure 8. the flip-flops are set by the negative edges of output signals of the dividers. the rising edge of the signal, l, will reset the flip-flops after both flip-flops have been set. around zero phase error this has the effect of delaying the reset for 1 reference input cycle. this avoids non-linearity or deadband around zero phase error. the flip-flops drive on-chip charge pumps. a source current from the charge pump indicates the vco frequency will be increased; a sink current indicates the vco frequency will be decreased.
philips semiconductors product specification SA7025 1ghz low-voltage fractional-n synthesizer 1996 aug 6 11 msb lsb word a1 a0 b c d e address bits test bits d31 d0 0 nf nm1 nm2 nm3 nm2 cn d0 0 nf nm1 nm2 nm3 nm2 d23 pr = a01o pr = a10o 1 0 0 0 cn ck cl pr 100 na 1 p a 101 nr 0sm e m sa e a f m o d l o n g 1111 d23 d0 0000 000 t 1 t 0 0 0 last in first in sr00605 figure 6. serial input word format current settings the SA7025 has 3 current setting pins: ra, rn and rf. the active charge pump currents and the fractional compensation currents are linearly dependent on the current connected between the current setting pin and v ss . the typical value r (current setting resistor) can be calculated with the formula: r v dda 0.9 150 i r i r the current can be set to zero by connecting the corresponding pin to v dda . auxiliary output charge pumps the auxiliary charge pumps on pin pha are driven by the auxiliary phase detector and the current value is determined by the external resistor ra at pin ra. the active charge pump current is typically: |i pha | 8 i ra main output charge pumps and fractional compensation currents the main charge pumps on pin php and phi are driven by the main phase detector and the current value is determined by the current at pin rn and via a number of dacs which are driven by registers of the serial input. the fractional compensation current is determined by the current at pin rf, the contents of the fractional accumulator frd and a number of dacs driven by registers from the serial input. the timing for the fractional compensation is derived from the reference divider. the current is on during 1 input reference cycle before and 1 cycle after the output signal to the phase comparator. figure 9 shows the waveforms for a typical case.
philips semiconductors product specification SA7025 1ghz low-voltage fractional-n synthesizer 1996 aug 6 12 table 1. function table symbol bits function nm1 12 number of main divider cycles when prescaler modulus = 64 * nm2 8 if pr = a01o 4 if pr = a10o number of main divider cycles when prescaler modulus = 65 * nm3 4 if pr = a10o number of main divider cycles when prescaler modulus = 72 * pr 2 prescaler type in use pr = a01o: modulus 2 prescaler (64/65) pr = a10o: modulus 3 prescaler (64/65/72) nf 3 fractional-n increment fmod 1 fractional-n modulus selection flag a1o: modulo 8 a0o: modulo 5 long 1 a word format selection flag a0o: 24 bit a0 format a1o: 32 bit a1 format cn 8 binary current setting factor for main charge pumps cl 2 binary acceleration factor for proportional charge pump current ck 4 binary acceleration factor for integral charge pump current em 1 main divider enable flag ea 1 auxiliary divider enable flag sm 2 reference select for main phase detector sa 2 reference select for auxiliary phase detector nr 12 reference divider ratio na 12 auxiliary divider ratio pa 1 auxiliary prescaler mode: pa = a0o: divide by 4 pa = a1o: divide by 1 * not including reset cycles and fractional-n effects. sa = a11o sa = a10o sa = a01o sa = a00o sm = a11o sm = a10o sm = a01o sm = a00o main select auxiliary select reference input divide by nr 2 main detector phase auxiliary detector phase 2 2 sr00606 figure 7. reference divider table 2. prescaler ratio the total division ratio from prescaler to the phase detector may be expressed as: if pr = a01o n = (nm1 + 2) x 64 + nm2 x 65 n' = (nm1 + 1) x 64 + (nm2 + 1) x 65 (*) if pr = a10o n = (nm1 + 2) x 64 + nm2 x 65 + (nm3 + 1) x 72 n' = (nm1 + 1) x 64 + (nm2 + 1) x 65 + (nm3 + 1) x 72 (*) (*) when the fractional accumulator overflows the prescaler ratio = 65 (64 + 1) and the total division ratio n' = n + 1
philips semiconductors product specification SA7025 1ghz low-voltage fractional-n synthesizer 1996 aug 6 13 table 3. pr modulus pr modulus prescaler bit capacity nm1 nm2 nm3 01 2 12 8 10 3 12 4 4 when the serial input a word is loaded, the output circuits are in the aspeed-up modeo as long as the strobe is h, else the anormal modeo is active. in the anormal modeo the current output php is: i php_n i php i php_comp where: |i php | cn i rn 32 :charge pump current |i php_comp | frd i rf 128 :fractional comp. current the current in phi is zero in anormal modeo. in aspeed-up modeo the current in output php is: i php_s i php i php_comp |i php | cn i rn 32 (2 cl 1 1) |i php_comp | frd i rf 128 (2 cl 1 1) in aspeed-up modeo the current in output phi is: i phi_s i phi i phi_comp where: |i phi | i rn cn 32 (2 cl 1 )ck |i phi_comp | i rf frd 128 (2 cl 1 )ck figure 9 shows that for proper fractional compensation, the area of the fractional compensation current pulse must be equal to the area of the charge pump ripple output. this means that the current setting on the input rn, rf is approximately: i rn i rf (q f vco ) (3 cn f inr ) where: q = fractional-n modulus f vco = f inm n, input frequency of the prescaler f inr = input frequency of the reference divider phi pump is meant for switching only. current and compensation are not as accurate as php. ref_in reference divider aux/main divider l a1o r d c q r d c q r a1o x p n n-type charge pump ph p-type charge pump v dda v ssa ref_in l r x p n i p h sr00607 figure 8. phase detector structure with timing
philips semiconductors product specification SA7025 1ghz low-voltage fractional-n synthesizer 1996 aug 6 14 reference r main n detector output contents accum. fractional compensation current n n n + 1 n n + 1 24130 pulse-width modulation output on php, phi pulse-level modulation ma m a time vco cycles sr00608 figure 9. waveforms for nf = 2, fraction = 0.4 lock detect the output lock is h when the auxiliary phase detector and the main phase detector indicates a lock condition. the lock condition is defined as a phase difference of less than +1 cycle on the reference input ref_in. the lock condition is also fulfilled when the relative counter is disabled (em = a0o or respectively ea = a0o) for the main, respectively auxiliary counter. test modes the lock output is selectable as f ref , f aux , f main and lock. bits t1 and t0 of the e word control the selection (see figures 6 and 10). if t1 = t0 = low, or if the e-word is not sent, the lock output is configured as the normal lock output described in the lock detect section. if t1 = low and t0 = high, the lock output is configured as f ref . the signal is the buffered output of the reference divider nr and the 3-bit binary counter sm. the f ref signal appears as normally low and pulses high whenever the divider reaches terminal count from the value programmed into the nr and sm registers. the f ref signal can be used to verify the divide ratio of the reference divider. if t1 = high and t0 = low, the lock output is configured as f aux . the signal is normally high and pulses low whenever the divider reaches terminal count from the value programmed into the na and pa registers. the f aux signal can be used to verify the divide ratio of the auxiliary divider. if t1 = high and t0 = high, the lock output is configured as f main . the signal is the buffered output of the main divider. the f main signal appears as normally high and pulses low whenever the divider reaches terminal count from the value programmed into the nm1, nm2 or nm3 registers. the f main signal can be used to verify the divide ratio of the main divider and the prescaler.
philips semiconductors product specification SA7025 1ghz low-voltage fractional-n synthesizer 1996 aug 6 15 test pin the test pin, pin 19, is a buffered logic input which is exclusively ored with the output of the prescaler. the output of the xor gate is the input to the main divider. the test pin must be connected to v dd during normal operation as a synthesizer. this pin can be used as an input for verifying the divide ratio of the main divider; while in this condition the input to the prescaler, rf in , may be connected to v ccp through a 10k w resistor in order to place prescaler output into a known state. main divider ref divider aux divider sm lock t1 t0 f main f aux select logic sr00609 figure 10. test mode diagram pin functions 5 pin no. pin mnemonic dc v equivalent circuit pin no. pin mnemonic dc v equivalent circuit 1 clock 2data 18 lock 3 strobe 19 test 5rf in 2.1 v dd v ss 6 6rf in 2.1 2.5k 2.5k v ccp = 3v v ss 10 100k 8 ref in 1.8 10 aux in 1.8 v dda = 3v v ss enable 9 ra 1.35 16 rn 1.35 17 rf 1.35 v dda = 3v v ssa 25 m a 9 11 pha 13 phi 14 php v dda v ssa 11 18 v dd v ss 1 sr00610 figure 11. pin functions
philips semiconductors product specification SA7025 1ghz low-voltage fractional-n synthesizer 1996 aug 6 16 typical performance characteristics t = 40 c t = 25 c t = 85 c supply voltage (v) v ccp = v dda = v dd em = ea = 1, note5 11 2.7 3.5 4.5 5.5 i total (ma) 10 9 8 7 6 5 sr00611 figure 12. operational supply current vs supply voltage and temperature supply voltage (v) v ccp = v dda = v dd ea=0, em=1, note5 7 2.7 3.5 4.5 5.5 i total (ma) 6 5 4 3 2 1 t = 40 c t = 25 c t = 85 c sr00612 figure 13. auxiliary operational supply current vs supply voltage and temperature 2.7v 3.5v 4.5v 5.5v t a = 25 c, n = 3971.625 v dd = v ccp frequency (mhz) 20 500 input power (dbm) 0 20 40 60 550 600 650 700 750 800 850 900 950 1000 1050 1100 1150 sr00613 figure 14. main divider input power vs frequency and supply supply voltage (v) v ccp = v dda = v dd ea=0, em=1, note5 8.5 8 7.5 7 6.5 6 5.5 5 4.5 4 2.7 3.5 4.5 5.5 i total (ma) t = 40 c t = 25 c t = 85 c sr00614 figure 15. main operational supply current vs supply voltage and temperature auxiliary input frequency (mhz) v dd = 3v, v dda = 5v pin = 10dbm, ref divider halted 3.5 50 100 150 i total (ma) 3 2.5 2 1.5 1 t = 40 c t = 25 c t = 85 c sr00615 figure 16. auxiliary operational supply current vs frequency and temperature t=40 c t=25 c t=85 c v dd = v ccp = 3v n=3971.625 frequency (mhz) 20 500 input power (dbm) 0 20 40 60 550 600 650 700 750 800 850 900 950 1000 1050 1100 1150 sr00616 figure 17. main divider input power vs frequency and temperature
philips semiconductors product specification SA7025 1ghz low-voltage fractional-n synthesizer 1996 aug 6 17 typical performance characteristics (continued) 3/3v 3/5v 5/5v n=100 v dd /v dda 10 15 20 25 30 35 40 45 50 55 0 5 10 15 20 25 30 input power (dbm) frequency (mhz) sr00617 figure 18. reference divider minimum input power vs frequency and supply minimum input power (dbm) t a =amb, pa=1, n=100 30 50 70 90 110 130 150 frequency (mhz) 0 5 10 15 20 25 30 v dd /v dda 3/3v 3/5v 5/5v sr00618 figure 19. auxiliary divider minimum input power vs frequency and supply t a = amb, pa=0, n=25 50 100 150 200 250 frequency (mhz) 0 v dd /v dda 5 10 15 20 25 30 minimum input power (dbm) 3/3v 3/5v 5/5v figure 20. auxiliary divider minimum input power vs frequency and supply 10 15 20 25 30 35 40 5 minimum input powe (dbm) frequency (dbm) 0 5 10 15 20 v dd = 3v, v dda = 5v, n = 100 t = 40 c t = 25 c t = 85 c sr00631 figure 21. reference divider minimum input power vs frequency and temperature v dd =3v, v dda =5v, pa=1, n=100 30 50 70 90 frequency (mhz) 10 15 20 25 minimum input power (dbm) t = 40 c t = 25 c t = 85 c sr00632 figure 22. auxiliary divider minimum input power vs frequency and temperature v dd =3v, v dda =5v 50 100 150 200 frequency (mhz) 0 5 10 15 20 minimum input power (dbm) t = 40 c t = 25 c t = 85 c pa=0, n=25 sr00619 figure 23. auxiliary divider minumum input power vs frequency and temperature
philips semiconductors product specification SA7025 1ghz low-voltage fractional-n synthesizer 1996 aug 6 18 50 300 600 900 1100 j1 j2 j2 j1 j0.5 0 j0.5 r3 l4 c2 r1 c1 0.1pf 0.85pf 3000 w 1 w 2nh equivalent input impedance 1 v ccp = v dd = 3v t a = 25 c sr00620 figure 24. typical rf in input impedance
philips semiconductors product specification SA7025 1ghz low-voltage fractional-n synthesizer 1996 aug 6 19 top silk screen top view bottom view sr00621 figure 25. SA7025dk demoboard layout (not actual size)
philips semiconductors product specification SA7025 1ghz low-voltage fractional-n synthesizer 1996 aug 6 20 sr00622 figure 26. SA7025dk application circuit
philips semiconductors product specification SA7025 1ghz low-voltage fractional-n synthesizer 1996 aug 6 21 ssop20: plastic shrink small outline package; 20 leads; body width 4.4 mm sot266-1
philips semiconductors product specification SA7025 low-voltage 1ghz fractional-n synthesizer
philips semiconductors and philips electronics north america corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performanc e. philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under a ny patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copy right, or mask work right infringement, unless otherwise specified. applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. life support applications philips semiconductors and philips electronics north america corporation products are not designed for use in life support appl iances, devices, or systems where malfunction of a philips semiconductors and philips electronics north america corporation product can reasonab ly be expected to result in a personal injury. philips semiconductors and philips electronics north america corporation customers using or sel ling philips semiconductors and philips electronics north america corporation products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors and philips electronics north america corporation for any damages resulting from such improper use or sale. this data sheet contains preliminary data, and supplementary data will be published at a later date. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. philips semiconductors 811 east arques avenue p.o. box 3409 sunnyvale, california 940883409 telephone 800-234-7381 definitions data sheet identification product status definition objective specification preliminary specification product specification formative or in design preproduction product full production this data sheet contains the design target or goal specifications for product development. specifications may change in any manner without notice. this data sheet contains final specifications. philips semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. philips semiconductors and philips electronics north america corporation register eligible circuits under the semiconductor chip protection act. ? copyright philips electronics north america corporation 1996 all rights reserved. printed in u.s.a. print code document order number:

▲Up To Search▲

Price & Availability of SA7025

	To Download SA7025 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .